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2-73 as4lc4m4 austin semiconductor, inc., reserves the right to change products or specifications without notice. rev. 11/97 ds000022 as4lc4m4 883c 4 meg x 4 dram austin semiconductor, inc. dram available in military specifications ? mil-std-883 ? smd planned features ? industry-standard x4 pinout, timing, functions and packages ? high-performance cmos silicon-gate process ? single +3.3v 0.3v power supply ? low power, 1mw standby; 150mw active, typical ? all inputs, outputs and clocks are ttl-compatible ? refresh modes: ? r ? a / s only, ? c ? a / s-before- ? r ? a / s (cbr) hidden ? 2,048-cycle (11 row-, 11 column-addresses) ? extended data-out (edo) page access cycle ? 5v-tolerant i/os (5.5v maximum v ih level) options marking ? timing 60ns access (contact factory) -6 70ns acess -7 80ns access -8 ? packages ceramic soj ecj no. 505 ceramic lcc ec no. 212 ceramic gull wing ecg no. 603 pin assignment (top view) 24/28-pin 1 2 3 4 5 6 8 9 10 11 12 13 26 25 24 23 22 21 19 18 17 16 15 14 a logic high on ? w / e dictates read mode while a logic low on ? w / e dictates write mode. during a write cycle, data-in (d) is latched by the falling edge of ? w / e or / c / a / s, whichever occurs last. an early write occurs when ? w / e is taken low prior to / c / a / s falling. a late write or read-modify-write occurs when ? w / e falls after / c / a / s was taken low. during early write cycles, the data- outputs (q) will remain high-z regardless of the state of ? o / e. during late write or read-modify-write cycles, ? o / e must be taken high to disable the data-outputs prior to applying input data. if a late write or read-modify- write is attempted while keeping ? o / e low, no write will occur, and the data-outputs will drive read data from the accessed location. the four data inputs and the four data outputs are routed through four pins using common i/o, and pin direction is controlled by ? w / e and ? o / e. fast page mode fast page operations allow faster data operations (read, write or read-modify-write) within a row- address-defined page boundary. the fast page cycle is always initiated with a row-address strobed-in by ? r ? a / s followed by a column-address strobed-in by ? c ? a / s. ? c ? a / s may be toggled-in by holding ? r ? a / s low and strobing-in differ- ent column-addresses, thus executing faster memory cycles. returning r ? a / s high terminates the fast page mode of operation. 4 meg x 4 dram 3.3v, edo page mode v cc dq1 dq2 / w / e / r / a / s nc a10 a0 a1 a2 a3 v cc v ss dq4 dq3 / c / a / s / o / e a9 a8 a7 a6 a5 a4 vss 1 2 3 4 5 6 9 10 11 12 13 14 28 27 26 25 24 23 20 19 18 17 16 15 general description the as4lc4m4 is a randomly accessed solid-state memory containing 16,777,216 bits organized in a x4 con- figuration. the as4lc4m4 ? r ? a / s is used to latch the first 11 bits and ? c ? a / s the latter 11 bits. read and write cycles are selected with the ? w / e input. a logic high on ? w / e dictates read mode while a logic low on ? w / e dictates write mode. during a write cycle, data-in (d) is latched by the falling edge of ? w / e or ? c ? a / s, whichever occurs last. if ? w / e goes low prior to ? c ? a / s going low, the output pins remain open (high- z) until the next ? c ? a / s cycle, regardless of ? o / e. key timing parameters speed t rc t rac t pc t aa t cac t cas -6 110ns 60ns 30ns 30ns 15ns 12ns -7 130ns 70ns 35ns 35ns 18ns 15ns -8 150ns 80ns 40ns 40ns 20ns 20ns
2-74 as4lc4m4 austin semiconductor, inc., reserves the right to change products or specifications without notice. rev. 11/97 ds000022 as4lc4m4 883c 4 meg x 4 dram austin semiconductor, inc. ? r ? a / s and ? c ? a / s are low, data will toggle from valid data to high-z and back to the same valid data. if ? o / e is toggled or pulsed after ? c ? a / s goes high while ? r ? a / s remains low, data will transition to and remain high-z (refer to figure 1). ? w / e can also perform the function of disabling the output devices under certain conditions, as shown in figure 2. during an application, if the dq outputs are wire ord, ? o / e must be used to disable idle banks of drams. alterna- tively, pulsing ? w / e to the idle banks during ? c ? a / s high time will also high-z the outputs. independent of ? o / e control, the outputs will disable after t off, which is referenced from the rising edge of ? r ? a / s or ? c ? a / s, whichever occurs last. edo page mode the as4lc4m4e8 provides edo page mode which is an accelerated fast page mode cycle. the primary advantage of edo is the availability of data-out even after ? c ? a / s returns high. edo allows ? c ? a / s precharge time ( t cp) to occur without the output data going invalid. this elimi- nation of ? c ? a / s output control allows pipeline reads. fast-page-mode drams have traditionally turned the output buffers off (high-z) with the rising edge of ? c ? a / s. edo-page-mode drams operate similarly to fast-page-mode drams, except data will remain valid or become valid after ? c ? a / s goes high during reads, provided ? r ? a / s and ? o / e are held low. if ? o / e is pulsed while v v ih il cas v v ih il ras v v ih il addr row column (a) column (b) v v ih il oe v v ioh iol open dq t od valid data (b) valid data (a) column (c) valid data (a) t oe valid data (c) column (d) valid data (d) t od t oehc t od t oep t oes the dqs go back to low-z if t oes is met. the dqs remain high-z until the next cas cycle if t oehc is met. the dqs remain high-z until the next cas cycle if t oep is met. figure 1 output enable and disable
2-75 as4lc4m4 austin semiconductor, inc., reserves the right to change products or specifications without notice. rev. 11/97 ds000022 as4lc4m4 883c 4 meg x 4 dram austin semiconductor, inc. refresh preserve correct memory cell data by maintaining power and executing a ? r ? a / s cycle (read, write) or ? r ? a / s refresh cycle ( ? r ? a / s only, cbr, or hidden) so that all 2,048 combinations of ? r ? a / s addresses are executed at least every 32ms, regardless of sequence. the cbr refresh cycle will invoke the refresh counter for automatic ? r ? a / s addressing. v v ih il cas v v ih il ras v v ih il addr row column (a) don?t care undefined v v ih il we v v ioh iol open dq t wpz the dqs go to high-z if we falls, and if t wpz is met, will remain high-z until cas goes low with we high (i.e., until a read cycle is initiated). v v ih il oe valid data (b) t whz we may be used to disable the dqs to prepare for input data in an early write cycle. the dqs will remain high-z until cas goes low with we high (i.e., until a read cycle is initiated). t whz column (d) valid data (a) column (b) column (c) input data (c) figure 2 ?? ?? ? w // // / e control of dqs
2-76 as4lc4m4 austin semiconductor, inc., reserves the right to change products or specifications without notice. rev. 11/97 ds000022 as4lc4m4 883c 4 meg x 4 dram austin semiconductor, inc. functional block diagram 2048 2048 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 ras 11 11 11 no. 2 clock generator refresh controller no. 1 clock generator v dd vss 11 we cas 10 column- address buffer(11) row- address buffers (11) 2048 row decoder 2048 1024 column decoder oe dq1 dq2 dq3 dq4 4 4 4 4 refresh counter 1 row transfer (1 of 2) row transfer (1 of 2) 1024 4096 x 1024 x 4 memory array sense amplifiers i/o gating data-out buffer data-in buffer complement select 2048 row select (2 of 4096) truth table addresses data-in/out function ? r ? a / s ? c ? a / s ? w / e ? o / e t r t c dq1-dq4 standby h h > xxxxx high-z read l l h l row col data-out early write l l l x row col data-in read write l l h > ll > h row col data-out, data-in edo-page-mode 1st cycle l h > l h l row col data-out read 2nd cycle l h > l h l n/a col data-out edo-page-mode 1st cycle l h > l l x row col data-in early-write 2nd cycle l h > l l x n/a col data-in any cycle l l > h h l n/a n/a data-out edo-page-mode 1st cycle l h > lh > ll > h row col data-out, data-in read-write 2nd cycle l h > lh > ll > h n/a col data-out, data-in hidden read l > h > l l h l row col data-out refresh write l > h > l l l x row col data-in ? r ? a / s-only refresh l h x x row n/a high-z cbr refresh h > l l h x x x high-z
2-77 as4lc4m4 austin semiconductor, inc., reserves the right to change products or specifications without notice. rev. 11/97 ds000022 as4lc4m4 883c 4 meg x 4 dram austin semiconductor, inc. absolute maximum ratings* voltage on v cc pin relative to v ss ................. -1v to +4.6v voltage on nc, inputs or i/o pins relative to v ss .................................................... -1v to +5.5v operating temperature, t a (ambient) .. ta(min) = -55 c ................................................................... tc (max) = 125 c storage temperature ................................... -55 c to +150 c power dissipation ............................................................. 1w short circuit output current ..................................... 50ma *stresses greater than those listed under absolute maxi- mum ratings may cause permanent damage to the de- vice. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating condi- tions for extended periods may affect reliability. electrical characteristics and recommended dc operating conditions (notes: 1, 6, 7) (v cc = +3.3v 0.3v) parameter/condition symbol min max units notes supply voltage v cc 3.0 3.6 v input high (logic 1) voltage, all inputs (including nc pins) v ih 2.0 vcc+1 v input low (logic 0) voltage, all inputs (including nc pins) v il -1.0 0.8 v input leakage current any input 0v v in 5.5v vcc = 3.6v i i -2 2 m a (all other pins not under test = 0v) (nc pins not tested) output leakage current (q is disabled; 0v v out 5.5v) vcc=3.6v i oz -10 10 m a output levels v oh 2.4 v output high voltage (i out = -2ma) output low voltage (i out = 2ma) v ol 0.4 v parameter/condition sym -6 -7 -8 units notes standby current: (ttl) i cc 1 222ma ( ? r ? a / s = ? c ? a / s = v ih ) standby current: (cmos) i cc 2 111ma ( ? r ? a / s = ? c ? a / s = other inputs = v cc -0.2v operating current: random read/write average power supply current i cc 3 120 110 100 ma 3, 4, 12 ( ? r ? a / s, ? c ? a / s, address cycling: t rc = t rc [min]) operating current: edo page mode average power supply current i cc 4 110 100 90 ma 3, 4, 12 ( ? r ? a / s = v il , ? c ? a / s, address cycling: t pc = t pc [min]) refresh current: ? r ? a / s only average power supply current i cc 5 120 110 100 ma 3, 12 ( ? r ? a / s cycling, ? c ? a / s = v ih : t rc = t rc [min]) refresh current: cbr average power supply current i cc 6 120 110 100 ma 3, 5 ( ? r ? a / s, ? c ? a / s, address cycling: t rc = t rc [min]) max
2-78 as4lc4m4 austin semiconductor, inc., reserves the right to change products or specifications without notice. rev. 11/97 ds000022 as4lc4m4 883c 4 meg x 4 dram austin semiconductor, inc. capacitance parameter symbol max units notes input capacitance: address pins c i 1 7pf2 input capacitance: ? r ? a / s, ? c ? a / s, ? w / e, ? o / ec i 2 7pf2 input/output capacitance: dq c io 8pf2 electrical characteristics and recommended ac operating conditions (notes: 6, 7, 8, 9, 10, 11, 12, 13) (v cc = +3.3v 0.3v) ac characteristics -6 -7 -8 parameter sym min max min max min max units notes access time from column-address t aa 30 35 40 ns column-address set-up to ? c ? a / s precharge during write t ach 15 15 20 ns column-address hold time (referenced to ? r ? a / s) t ar 45 55 60 ns column-address setup time t asc 0 0 0 ns row-address setup time t asr 0 0 0 ns column-address to ? w / e delay time t awd 55 65 65 ns 20 access time from ? c ? a / s t cac 15 20 20 ns 14 column-address hold time t cah 10 15 15 ns ? c ? a / s pulse width t cas 12 10,000 15 10,000 20 10,000 ns ? c ? a / s hold time (cbr refresh) t chr 10 15 15 ns 5 ? c ? a / s to output in low-z t clz 0 0 0 ns data output hold after next ? c ? a / s low t coh 5 5 5 ns ? c ? a / s precharge time t cp 10 10 10 ns 15 access time from ? c ? a / s precharge t cpa 35 40 40 ns ? c ? a / s to ? r ? a / s precharge time t crp 5 5 5 ns ? c ? a / s hold time t csh 50 55 60 ns ? c ? a / s setup time (cbr refresh) t csr 5 5 10 ns 5 ? c ? a / s to ? w / e delay time t cwd 35 40 45 ns 20 write command to ? c ? a / s lead time t cwl 15 15 20 ns data-in hold time t dh 10 12 15 ns 21 data-in hold time (referenced to ? r ? a / s) t dhr 40 56 55 ns data-in setup time t ds 0 0 0 ns 21 output disable t od 015015 20 ns output enable t oe 15 20 20 ns 22 ? o / e hold time from ? w / e during read-modify-write cycle t oeh 10 12 15 ns ? o / e high hold from ? c ? a / s high t oehc 10 10 10 ns ? o / e high pulse width t oep 10 10 10 ns ? o / e low to ? c ? a / s high setup time t oes 5 5 5 ns
2-79 as4lc4m4 austin semiconductor, inc., reserves the right to change products or specifications without notice. rev. 11/97 ds000022 as4lc4m4 883c 4 meg x 4 dram austin semiconductor, inc. electrical characteristics and recommended ac operating conditions (notes: 6, 7, 8, 9, 10, 11, 12, 13) (v cc = +3.3v 0.3v) ac characteristics -6 -7 -8 parameter sym min max min max min max units notes output buffer turn-off delay t off 0 15 0 15 0 20 ns ? o / e setup prior to ? r ? a / s during hidden refresh cycle t ord 0 0 0 ns 19 edo-page-mode read or write cycle time t pc 30 35 40 ns edo-page-mode read-write cycle time t prwc 75 85 90 ns access time from ? r ? a / s t rac 60 70 80 ns 13 ? r ? a / s to column-address delay time t rad 15 30 15 35 15 40 ns 17 row-address hold time t rah 10 10 10 ns column-address to ? r ? a / s lead time t ral 30 35 40 ns ? r ? a / s pulse width t ras 60 10,000 70 10,000 80 10,000 ns ? r ? a / s pulse width (edo page mode) t rasp 60 100,000 70 100,000 80 100,00 ns random read or write cycle time t rc 110 130 150 ns ? r ? a / s to ? c ? a / s delay time t rcd 16 45 16 50 20 60 ns 16 read command hold time (referenced to ? c ? a / s) t rch 0 0 0 ns 18 read command setup time t rcs 0 0 0 ns refresh period (2,048 cycles) t ref 32 32 32 ms ? r ? a / s precharge time t rp 40 50 60 ns ? r ? a / s to ? c ? a / s precharge time t rpc 5 5 5 ns read command hold time (referenced to ? r ? a / s) t rrh 0 0 0 ns 18 ? r ? a / s hold time t rsh 13 15 15 ns read write cycle time t rwc 150 180 200 ns ? r ? a / s to ? w / e delay time t rwd 80 90 105 ns 20 write command to ? r ? a / s lead time t rwl 15 15 20 ns transition time (rise or fall) t t 2 30 2 30 2 30 ns write command hold time t wch 10 12 15 ns write command hold time (referenced to ? r ? a / s) t wcr 40 56 60 ns ? w / e command setup time t wcs 0 0 0 ns 20 output disable delay from ? w / e t whz 0 14 0 16 0 20 ns write command pulse width t wp 10 12 15 ns ? w / e pulse to disable at ? c ? a / s high t wpz 10 12 15 ns ? w / e hold time (cbr refresh) t wrh 10 10 10 ns 24 ? w / e setup time (cbr refresh) t wrp 10 10 10 ns 24
2-80 as4lc4m4 austin semiconductor, inc., reserves the right to change products or specifications without notice. rev. 11/97 ds000022 as4lc4m4 883c 4 meg x 4 dram austin semiconductor, inc. notes 1. all voltages referenced to v ss . 2. this parameter is sampled. v cc = +3.3v; f = 1 mhz. 3. i cc is dependent on cycle rates. 4. i cc is dependent on output loading and cycle rates. specified values are obtained with minimum cycle time and the outputs open. 5. enables on-chip refresh and address counters. 6. the minimum specifications are used only to indicate cycle time at which proper operation over the ful temperature range is assured. 7. an initail pause of 100 m s is required after power-up followed by eight / r / a / s refresh cycles ( / r / a / s only or cbr with / w / e high) before proper device operation is assured. the eight / r / a / s cycle wake-ups should be repeated any thime the t ref refresh requirement is exceeded. 8. ac characteristics assume t t = 2.5ns. 9. v ih (min) and v il (max) are reference levels for measuring timing of input signals. transition times are measured between v ih and v il (or between v il and v ih ). 10. in addition to meeting the transition rate specifica- tion, all input signals must transit between v ih and v il (or between v il and v ih ) in a monotonic manner. 11. column address changed once each cycle. 12. measured with a load equivalent to two ttl gates, 100pf and v ol = 0.8v and v oh = 2.0v. 13. assumes that t rcd < t rcd (max). if t rcd is greater than the maximum recommended value shown in this table, t rac will increase by the amount that t rcd exceeds the value shown. 14. assumes that t rcd 3 t rcd (max). 15. if ? c ? a / s is low at the falling edge of ? r ? a / s, q will be maintained from the previous cycle. to initiate a new cycle and clear the data-out buffer, ? c ? a / s must be pulsed high for t cp. 16. operation within the t rcd (max) limit ensures that t rac (max) can be met. t rcd (max) is specified as a reference point only; if t rcd is greater than the specified t rcd (max) limit, then access time is controlled exclusively by t cac, provided t rad is not exceeded. 17. operation within the t rad (max) limit ensures that t rac (min) and t cac (min) can be met. t rad (max) is specified as a reference point only; if t rad is greater than the specified t rad (max) limit, then access time is controlled exclusively by t aa, provided t rcd is not exceeded. 18. either t rch or t rrh must be satisfied for a read cycle. 19. t off (max) defines the time at which the output achieves the open circuit condition, and is not referenced to v oh or v ol . it is referenced from the rising edge of ? r ? a / s or ? c ? a / s, whichever occurs last. 20. t wcs, t rwd, t awd and t cwd are not restrictive operating parameters. t wcs applies to early write cycles. t rwd, t awd and t cwd apply to read-modify-write cycles. if t wcs 3 t wcs (min), the cycle is an early write cycle and the data output will remain an open circuit throughout the entire cycle. if t wcs < t wcs (min) and t rwd 3 t rwd (min), t awd 3 t awd (min) and t cwd 3 t cwd (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell. if neither of the above conditions is met, the state of data-out is indeterminate. ? o / e held high and ? w / e taken low after ? c ? a / s goes low results in a late write ( ? o / e-controlled) cycle. t wcs, t rwd, t cwd and t awd are not applicable in a late write cycle. 21. these parameters are referenced to ? c ? a / s leading edge in early write cycles and ? w / e leading edge in late write or read-modify-write cycles. 22. if ? o / e is tied permanently low, late write or read-modify-write operations are not permis- sible and should not be attempted. additionally, ? w / e must be pulsed during ? c ? a / s high time in order to place i/o buffers in high-z. 23. a hidden refresh may also be performed after a write cycle. in this case, ? w / e = low and ? o / e = high. 24. t wts and t wth are setup and hold specifications for the / w / e pin being held low to enable the jedec test mode (with cbr timing constraints). these two parameters are the inverts of t wrp and t wrh in the cbr refresh cycle.
2-81 as4lc4m4 austin semiconductor, inc., reserves the right to change products or specifications without notice. rev. 11/97 ds000022 as4lc4m4 883c 4 meg x 4 dram austin semiconductor, inc. read cycle t rrh t clz t cac t rac t aa valid data open t off t rch row t rcs t asc t rah t rad t ar t cah t ral t rcd t cas t rsh t csh t rp t rc t ras t crp t asr row open ras v v ih il v v ih il addr v v ih il dq v v oh ol v v ih il t od t oe oe v v ih il column cas we note 1 note 2 t wrp t wrh t ach don?t care undefined note: 1. although ? w / e is a dont care at ? r ? a / s time during an access cycle (read or write), the system designer should implement ? w / e high for t wrp and t wrh. this design implementation will facilitate compatibility with future edo drams. 2. t off is referenced from rising edge of ? r ? a / s or ? c ? a / s, whichever occurs last. timing parameters -6 -7 -8 sym min max min max min max units t aa 30 35 40 ns t ach 15 15 20 ns t ar 45 50 60 ns t asc 0 0 0 ns t asr 0 0 0 ns t cac 15 20 20 ns t cah 10 15 15 ns t cas 12 10,000 15 10,000 20 10,000 ns t clz 0 0 0 ns t crp 5 5 5 ns t csh 50 55 60 ns t od 0 15 0 15 20 ns t oe 15 20 20 ns t off015015020ns -6 -7 -8 sym min max min max min max units t rac 60 70 80 ns t rad 15 30 15 35 15 40 ns t rah 10 10 10 ns t ral 30 35 40 ns t ras 60 10,000 70 10,000 80 10,000 ns t rc 110 130 150 ns t rcd 16 45 16 50 20 60 ns t rch 0 0 0 ns t rcs 0 0 0 ns t rp 40 50 60 ns t rrh 0 0 0 ns t rsh 10 12 15 ns t wrh 10 10 10 ns t wrp 10 10 10 ns
2-82 as4lc4m4 austin semiconductor, inc., reserves the right to change products or specifications without notice. rev. 11/97 ds000022 as4lc4m4 883c 4 meg x 4 dram austin semiconductor, inc. timing parameters -6 -7 -8 sym min max min max min max units t ach 15 15 20 ns t ar 45 55 60 ns t asc 0 0 0 ns t asr 0 0 0 ns t cah 10 15 15 ns t cas 12 10,000 15 10,000 20 10,000 ns t crp 5 5 5 ns t csh 50 55 60 ns t cwl 15 15 20 ns t dh 10 12 15 ns t dhr 40 50 55 ns t ds 0 0 0 ns t rad 15 30 15 35 15 40 ns t rah 10 10 10 ns early write cycle don? care undefined v v ih il valid data row column row t ds t dhr t wp t wch t wcs t wcr t rwl t cwl t cah t asc t rah t asr t rad t ral t ar t cas t rsh t csh t rcd t crp t ras t rc t rp v v ih il addr v v ih il v v ih il dq v v ioh iol v v ih il ras oe t dh we cas t ach note 1 t wrp t wrh note: 1. although ? w / e is a dont care at ? r ? a / s time during an access cycle (read or write), the system designer should implement ? w / e high for t wrp and t wrh. this design implementation will facilitate compatibility with future edo drams. -6 -7 -8 sym min max min max min max units t ral 30 35 40 ns t ras 60 10,000 70 10,000 80 10,000 ns t rc 110 130 150 ns t rcd 16 45 16 50 20 60 ns t rp 40 50 60 ns t rsh 13 15 0 ns t rwl 15 15 20 ns t wch 10 12 15 ns t wcr 40 50 60 ns t wcs 0 0 0 ns t wp 10 12 15 ns t wrh 10 10 10 ns t wrp 10 10 10 ns
2-83 as4lc4m4 austin semiconductor, inc., reserves the right to change products or specifications without notice. rev. 11/97 ds000022 as4lc4m4 883c 4 meg x 4 dram austin semiconductor, inc. read write cycle (late write and read-modify-write cycles) valid d out valid d in row column row v v ih il v v ih il addr v v ih il v v ih il dq v v ioh iol v v ih il ras open open t oe t od t cac t rac t aa t clz t ds t dh t awd t wp t rwl t cwl t cwd t rwd t rcs t asc t cah t ar t asr t rad t ral t crp t rcd t cas t rsh t csh t ras t rwc t rp t rah oe t oeh we t ach cas note 1 t wrp t wrh don?t care undefined note: 1. although ? w / e is a dont care at ? r ? a / s time during an access cycle (read or write), the system designer should implement ? w / e high for t wrp and t wrh. this design implementation will facilitate compatibility with future edo drams. t oe 15 20 20 ns t oeh 10 12 15 ns t rac 60 70 80 ns t rad 15 30 15 35 15 40 ns t rah 10 10 10 ns t ral 30 35 40 ns t ras 60 10,000 70 10,000 80 10,000 ns t rcd 16 45 16 50 20 60 ns t rcs 0 0 0 ns t rp 40 50 60 ns t rsh 13 15 15 ns t rwc 150 180 200 ns t rwd 80 90 105 ns t rwl 15 15 20 ns t wp 10 12 15 ns t wrh 10 10 10 ns t wrp 10 10 10 ns timing parameters -6 -7 -8 sym min max min max min max units t aa 30 35 40 ns t ach 15 15 20 ns t ar 45 55 60 ns t asc 0 0 0 ns t asr 0 0 0 ns t awd 55 65 65 ns t cac 15 20 20 ns t cah 10 15 15 ns t cas 12 10,000 15 10,000 20 10,000 ns t clz 0 0 0 ns t crp 5 5 5 ns t csh 50 55 60 ns t cwd 35 40 45 ns t cwl 15 15 20 ns t dh 10 12 15 ns t ds 0 0 0 ns t od015 015020 ns -6 -7 -8 sym min max min max min max units
2-84 as4lc4m4 austin semiconductor, inc., reserves the right to change products or specifications without notice. rev. 11/97 ds000022 as4lc4m4 883c 4 meg x 4 dram austin semiconductor, inc. edo-page-mode read cycle valid data valid data valid data column column column row row don?t care undefined t od t cah t asc t ral t cp t rsh t cp t cp t cas t rcd t crp t pc t csh t rasp t rp t cah t asc t cah t asc t ar t rah t rad t asr t rcs t rrh t rch t off t cac t cpa t aa t clz t cac t cpa t aa t cac t rac t aa t clz t oe t od t oe t od open open v v ih il v v ih il addr v v ih il v v ih il dq v v oh ol v v ih il ras oe t cas t cas cas we t coh t oep t oehc t oes t oes note 1 t wrp t wrh t ach t ach t ach note: 1. although ? w / e is a dont care at ? r ? a / s time during an access cycle (read or write), the system designer should implement ? w / e high for t wrp and t wrh. this design implementation will facilitate compatibility with future edo drams. sym min max min max min max units t oep 10 10 10 ns t oes 5 5 5 ns t off015 015020ns t pc 30 35 40 ns t rac 60 70 80 ns t rad 15 30 15 35 15 40 ns t rah 10 10 10 ns t ral 30 35 40 ns t rasp 60 100,000 70 100,000 80 100,000 ns t rcd 16 45 16 50 20 60 ns t rch 0 0 0 ns t rcs 0 0 0 ns t rp 40 50 60 ns t rrh 0 0 0 ns t rsh 13 15 15 ns t wrh 10 10 10 ns t wrp 10 10 10 ns timing parameters -6 -7 -8 sym min max min max min max units t aa 30 35 40 ns t ach 15 15 20 ns t ar 45 55 60 ns t asc 0 0 0 ns t asr 0 0 0 ns t cac 15 20 20 ns t cah 10 15 15 ns t cas 12 10,000 15 10,000 20 10,000 ns t clz 0 0 0 ns t coh 5 5 5 ns t cp 10 10 10 ns t cpa 35 40 40 ns t crp 5 5 5 ns t csh 50 55 60 ns t od015 015020ns t oe 15 20 20 ns t oehc 10 10 10 ns -6 -7 -8
2-85 as4lc4m4 austin semiconductor, inc., reserves the right to change products or specifications without notice. rev. 11/97 ds000022 as4lc4m4 883c 4 meg x 4 dram austin semiconductor, inc. edo-page-mode early-write cycle t ds t dh t ds t dh t ds t dh t dhr t wcr valid data valid data valid data t rwl t wp t cwl t wch t wcs t wp t cwl t wch t wcs t wp t cwl t wch t wcs t cah t asc t ral t cah t asc t cah t asc t rah t asr t rad t ach t ach t ach t ar column column column row row t cp t cas t rsh t cp t cas t cp t cas t rcd t crp t pc t csh t rasp t rp v v ih il cas v v ih il addr v v ih il we v v ih il dq v v ioh iol ras oe v v ih il don?t care undefined note 1 t wrp t wrh note: 1. although ? w / e is a dont care at ? r ? a / s time during an access cycle (read or write), the system designer should implement ? w / e high for t wrp and t wrh. this design implementation will facilitate compatibility with future edo drams. sym min max min max min max units t rad 15 30 15 35 15 40 ns t rah 10 10 10 ns t ral 30 35 40 ns t rasp 60 100,000 70 100,000 80 100,00 ns t rcd 16 45 16 50 20 60 ns t rp 40 50 60 ns t rsh 13 15 15 ns t rwl 15 15 20 ns t wch 10 12 15 ns t wcr 40 50 60 ns t wcs 0 0 0 ns t wp 10 12 15 ns t wrh 10 10 10 ns t wrp 10 10 10 ns timing parameters -6 -7 -8 sym min max min max min max units t ach 15 15 20 ns t ar 45 55 60 ns t asc 0 0 0 ns t asr 0 0 0 ns t cah 10 12 15 ns t cas 12 10,000 15 10,000 20 10,000 ns t cp 10 10 10 ns t crp 5 5 5 ns t csh 50 55 60 ns t cwl 15 15 20 ns t dh 10 12 15 ns t dhr 40 50 55 ns t ds 0 0 0 ns t pc 30 35 40 ns -6 -7 -8
2-86 as4lc4m4 austin semiconductor, inc., reserves the right to change products or specifications without notice. rev. 11/97 ds000022 as4lc4m4 883c 4 meg x 4 dram austin semiconductor, inc. edo-page-mode read-write cycle (late write and read-modify-write cycles) don? care undefined t oe t oe t oe open d out valid d in valid d out valid d in valid d out valid d in valid open t dh t ds t aa t cpa t clz t cac t dh t ds t aa t cpa t clz t cac t dh t ds t aa t clz t cac t rac t wp t cwl t rwl t cwd t awd t wp t cwl t cwd t awd t wp t cwl t cwd t awd t rcs t rwd t asr t rah t asc t rad t ar t cah t asc t cah t asc t cah t ral t cp t cas t rsh t cp t rp t rasp t cas t cp t cas t rcd t csh t pc t crp row column column column row v v ih il cas v v ih il addr v v ih il v v ih il dq v v ioh iol v v ih il ras oe we t prwc t oeh t od t od t od note 2 t wrp t wrh note 1 note: 1. t pc is for late write cycles only. 2. although ? w / e is a dont care at ? r ? a / s time during an access cycle (read or write), the system designer should implement ? w / e high for t wrp and t wrh. this design implementation will facilitate compatibility with future edo drams. timing parameters -6 -7 -8 sym min max min max min max units t aa 30 35 40 ns t ar 45 55 60 ns t asc 0 0 0 ns t asr 0 0 0 ns t awd 55 65 65 ns t cac 15 20 20 ns t cah 10 15 15 ns t cas 12 10,000 15 10,000 20 10,000 ns t clz 0 0 0 ns t cp 10 10 10 ns t cpa 35 40 40 ns t crp 5 5 5 ns t csh 50 55 60 ns t cwd 35 40 45 ns t cwl 15 15 20 ns t dh 10 12 15 ns t ds 0 0 0 ns t od 0 15 0 15 0 20 ns -6 -7 -8 sym min max min max min max units t oe 15 20 20 ns t oeh 10 12 15 ns t pc 30 35 40 ns t prwc 75 85 90 ns t rac 60 70 80 ns t rad 15 30 15 35 15 40 ns t rah 10 10 10 ns t ral 30 35 40 ns t rasp 60 100,000 70 100,000 80 100,000 ns t rcd 16 45 16 50 20 60 ns t rcs 0 0 0 ns t rp 40 50 60 ns t rsh 13 15 15 ns t rwd 80 90 105 ns t rwl 15 15 20 ns t wp 10 12 15 ns t wrh 10 10 10 ns t wrp 10 10 10 ns
2-87 as4lc4m4 austin semiconductor, inc., reserves the right to change products or specifications without notice. rev. 11/97 ds000022 as4lc4m4 883c 4 meg x 4 dram austin semiconductor, inc. edo-page-mode read-early-write cycle (pseudo read-modify-write) v v ih il v v ih il ras v v ih il addr v v ih il we t rasp t rp row column (a) column (n) row v v ih il oe v v ioh iol t crp t csh t cas t rcd t asr t rah t rad t asc t ar t cah t asc t cah t asc t cah t ral t cp t rsh valid data in t rcs t rch t wcs t oe valid data (b) valid data (a) t whz t cac t cpa t aa t cac t aa open dq t pc rac t t coh t wch t ds t dh t pc column (b) t ach cas t cas t cas t cp t cp don?t care undefined note 1 t wrp t wrh note: 1. although ? w / e is a dont care at ? r ? a / s time during an access cycle (read or write), the system designer should implement ? w / e high for t wrp and t wrh. this design implementation will facilitate compatibility with future edo drams. sym min max min max min max units t pc 30 35 40 ns t rac 60 70 80 ns t rad 15 30 15 35 15 40 ns t rah 10 10 10 ns t ral 30 35 40 ns t rasp 60 100,000 70 100,000 80 100,000 ns t rcd 16 45 16 50 20 60 ns t rch 0 0 0 ns t rcs 0 0 0 ns t rp 40 50 60 ns t rsh 13 15 15 ns t wch 10 12 15 ns t wcs 0 0 0 ns t whz013 015015ns t wrh 10 10 10 ns t wrp 10 10 10 ns timing parameters -6 -7 -8 sym min max min max min max units t aa 30 35 40 ns t ach 15 15 20 ns t ar 45 55 60 ns t asc 0 0 0 ns t asr 0 0 0 ns t cac 15 20 20 ns t cah 10 15 15 ns t cas 12 10,000 15 10,000 20 10,000 ns t coh 5 5 5 ns t cp 10 10 10 ns t cpa 35 40 40 ns t crp 5 5 5 ns t csh 50 55 60 ns t dh 10 12 15 ns t ds 0 0 0 ns t oe 15 20 20 ns -6 -7 -8
2-88 as4lc4m4 austin semiconductor, inc., reserves the right to change products or specifications without notice. rev. 11/97 ds000022 as4lc4m4 883c 4 meg x 4 dram austin semiconductor, inc. read cycle (with ? w / e-controlled disable) t clz t cac t rac t aa valid data open t rch t rcs t asc t rah t rad t ar t cah t rcd t cas t csh t crp t asr row open ras v v ih il v v ih il addr v v ih il dq v v oh ol v v ih il t od t oe oe v v ih il column we t whz t wpz t cp t asc t rcs column t clz don?t care undefined note 1 t wrp t wrh cas note: 1. although ? w / e is a dont care at ? r ? a / s time during an access cycle (read or write), the system designer should implement ? w / e high for t wrp and t wrh. this design implementation will facilitate compatibility with future edo drams. sym min max min max min max units t oe 15 20 20 ns t rac 60 70 80 ns t rad 15 30 15 35 15 40 ns t rah 10 10 10 ns t rcd 16 45 16 50 20 60 ns t rch 0 0 0 ns t rcs 0 0 0 ns t whz014016020ns t wpz 10 12 15 ns t wrh 10 10 10 ns t wrp 10 10 10 ns -6 -7 -8 timing parameters -6 -7 -8 sym min max min max min max units t aa 30 35 40 ns t ar 45 55 60 ns t asc 0 0 0 ns t asr 0 0 0 ns t cac 15 20 20 ns t cah 10 15 15 ns t cas 12 10,000 15 10,000 20 10,000 ns t clz 0 0 0 ns t cp 10 10 10 ns t crp 5 5 5 ns t csh 50 55 60 ns t od 0 15 015020ns
2-89 as4lc4m4 austin semiconductor, inc., reserves the right to change products or specifications without notice. rev. 11/97 ds000022 as4lc4m4 883c 4 meg x 4 dram austin semiconductor, inc. timing parameters -6 -7 -8 sym min max min max min max units t asr 0 0 0 ns t chr 10 15 15 ns t cp 10 10 10 ns t crp 5 5 5 ns t csr 5 5 10 ns t rah 10 10 10 ns ?? ?? ? r ?? ?? ? a // // / s-only refresh cycle row v v ih il cas v v ih il addr v v ih il ras t rc t ras t rp t crp t asr t rah row open dq v v oh ol t rpc we v v ih il t wrh t wrp t wrh t wrp note 1 cbr refresh cycle (addresses and ? o / e = dont care) t rp v v ih il ras t ras open t chr t csr v v ih il v v oh ol cas dq t rp t ras t rpc t csr t rpc t chr t cp v v ih il t wrp t wrh t wrp t wrh we don?t care undefined note: 1. although ? w / e is a dont care at ? r ? a / s time during an access cycle (read or write), the system designer should implement ? w / e high for t wrp and t wrh. this design implementation will facilitate compatibility with future edo drams. sym min max min max min max units t ras 60 10,000 70 10,000 80 10,000 ns t rc 110 130 150 ns t rp 40 50 60 ns t rpc 5 5 5 ns t wrh 10 10 10 ns t wrp 10 10 10 ns -6 -7 -8
2-90 as4lc4m4 austin semiconductor, inc., reserves the right to change products or specifications without notice. rev. 11/97 ds000022 as4lc4m4 883c 4 meg x 4 dram austin semiconductor, inc. hidden refresh cycle 24 ( ? w / e = high; ? o / e = low) don? care undefined t clz t off open valid data open column row t cac t rac t aa t cah t asc t rah t asr t rad t ar t ral t crp t rcd t rsh t ras t rp t chr t ras dq v v oh ol v v ih il addr v v ih il v v ih il ras v v ih il t oe t od oe t ord cas sym min max min max min max units t off0 150150 20ns t ord 0 0 0 ns t rac 60 70 80 ns t rad 15 30 15 35 15 40 ns t rah 10 10 10 ns t ral 30 35 40 ns t ras 60 10,000 70 10,000 80 10,000 ns t rcd 16 45 16 50 20 60 ns t rp 40 50 60 ns t rsh 13 15 15 ns timing parameters -6 -7 -8 sym min max min max min max units t aa 30 35 40 ns t ar 45 55 60 ns t asc 0 0 0 ns t asr 0 0 0 ns t cac 15 20 20 ns t cah 10 15 15 ns t chr 10 15 15 ns t clz 0 0 0 ns t crp 5 5 5 ns t od 0 15 0 15 0 20 ns t oe 15 20 20 ns -6 -7 -8
2-91 as4lc4m4 austin semiconductor, inc., reserves the right to change products or specifications without notice. rev. 11/97 ds000022 as4lc4m4 883c 4 meg x 4 dram austin semiconductor, inc. electrical test requirements subgroups mil-std-883 test requirements (per method 5005, table i) interim electrical (pre-burn-in) test parameters 2, 8a, 10 (method 5004) final electrical test parameters 1*, 2, 3, 7*, 8, 9, 10, 11 (method 5004) group a test requirements 1, 2, 3, 4**, 7, 8, 9, 10, 11 (method 5005) group c and d end-point electrical parameters 1, 2, 3, 7, 8, 9, 10, 11 (method 5005) * pda applies to subgroups 1 and 7. ** subgroup 4 shall be measured only for initial qualification and after process or design changes, which may affect input or output capacitance.
2-92 as4lc4m4 austin semiconductor, inc., reserves the right to change products or specifications without notice. rev. 11/97 ds000022 as4lc4m4 883c 4 meg x 4 dram austin semiconductor, inc.

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